1. Field of the Invention
The present invention generally relates to a CDMA (Code Division Multiple Access) communication system, and more particularly to a CDMA receiver thereof.
2. Description of the Related Art
A CDMA communication system refers to a communication system in which a transmitter spreads a user signal to be transmitted with a spreading code and then transmits the signal, while a receiver despreads the received signal with a spreading code which is a complex conjugate number of the spreading code to obtain the original user signal. The user signal to be transmitted as information is hereinafter referred to as a symbol and a transmission speed of the user signal is hereinafter referred to as a symbol rate. A chip rate, which is a transmission speed of the spreading code for spreading the symbol, is typically several tens to several hundreds times higher than the symbol rate. A chip is a unit of data constituting the spreading code.
In the CDMA communication system, a plurality of transmitters perform spread with differing spreading codes each having orthogonality, and a receiver selects a spreading code for use in despread to be able to specify a signal from a transmitter with a channel established therebetween, thus making it possible to use the same frequency band for a plurality of channels.
In the communication system, since the receiver is unable to despread the received data unless it detects synchronization of it. Thus, the transmitter always transmits a pilot channel for the detection of the synchronization independently of a channel for the transmission of the user signal. The receiver detects the synchronization with the pilot channel to perform synchronous detection for other channel.
Next, the construction of such a prior art CDMA communication system will be described by way of example with reference to FIGS. 1 and 2. The prior art CDMA communication system comprises a CDMA transmitter and a CDMA receiver. FIG. 1 illustrates in block form a configuration of the CDMA transmitter, and FIG. 2 illustrates in block form a configuration of the CDMA receiver.
The CDMA transmitter in FIG. 1 transmits a user signal to a plurality of CDMA receivers over a signal frequency band, and comprises multipliers 11, 120 to 12n, and 15, an adder 14, and a transmission unit (TX RF) 16.
Multiplier 11 multiplies common pilot signal (P) 101 by spreading code Cp. Multipliers 120 to 12n multiply user signals (D0 to Dn) 1020 to 102n by spreading codes CD0 to CDn. Each of these spreading codes Cp and CD0 to CDn is a spreading code of a so-called short code. Adder 14 adds output signals from multiplier 11 and 120 to 12n together to perform code division multiplexing.
Multiplier 15 multiplies an output signal from adder 14 by spreading code CL to convert the output signal from adder 14 to a spread signal. The spreading code CL is a spreading code of a so-called long code. Transmission unit (TX RF) 16 modulates the spread signal generated by multiplier 15 and then amplifies the modulated signal for conversion to transmission signal 107.
In this means, the transmitter spreads n+1 user signals (D0 to Dn) 1020 to 102n to be transmitted with different spreading codes CD0 to CDn respectively for transmission.
As shown in FIG. 2, the CDMA receiver comprises a reception unit (RX RF) 21, multipliers 22, 51 and 61, high speed adders 52 and 62, and registers 53 and 63.
Reception unit (RX RF) 21 demodulates received signal 201. Multiplier 22 multiplies the signal demodulated by reception unit 21 by CL* which is complex conjugate number of spreading code CL for despread. Multiplier 51 multiplies the signal despread by multiplier 22 by CP* which is complex conjugate number of spreading code CP.
Multiplier 61 multiplies the signal despread by multiplier 22 by CDi* which is complex conjugate number of spreading code CDi (i=0 to n) assigned to each of user signals 1020 to 102n. For example, in the CDMA receiver for receiving user signal D2, the signal despread by multiplier 22 is multiplied by spreading code CD2* at multiplier 61.
Register 53 stores output signals from high speed adder 52 for one chip and then outputs the signals. High speed adder 52 adds an output signal from multiplier 51 to the output signal from register 53. In this means, high speed adder 52 and register 53 accumulate the output signal from multiplier 51 for one symbol period to thereby generate despread pilot signal 205.
Register 63 stores output signals from high speed adder 62 for one chip and then outputs the signals. High speed adder 62 adds an output signal from multiplier 61 to the output signal from register 63. In this means, high speed adder 62 and register 63 accumulate the output signal from multiplier 61 for one symbol period to thereby generate despread user signal 204.
Both registers 53 and 63 are designed to be cleared by a signal (not shown), after the completion of the accumulation of the signal for one symbol period of time.
The prior art CDMA receiver is intended for receiving only one of a plurality of channels transmitted, and therefore only one set of multiplier 61, high speed adder 62, and register 63 is shown in FIG. 2. However, the provision of a plurality of sets of these circuits enables a plurality of channels to be simultaneously received.
In the prior art CDAM receiver, since the data despread by multiplier 51 and the data despread by multiplier 61 both operate at a chip rate, a high speed adder capable of processing the signal at the chip rate is required to perform integration for these data for one symbol period in real time. To this end, the prior art CDMA receiver utilizes high speed adders 52 and 62 that consume a larger amount of power than a slow speed adder. This prior art CDMA receiver must use two high speed adders with a high power consumption.
However, when the CDMA communication system is applied to a mobile communication system, an increased power consumption will cause decrease in operating time because a mobile communication terminal operates with a power supply such as a battery. In particular, since the mobile communication terminal has been become increasingly smaller in recent years and a less capacity is available for a battery mounted in the mobile communication terminal, increase in the power consumption is a serious problem.
It is an object of the present invention to provide a CDMA receiver with a reduced number of required high speed adders and therefore has a less amount of power consumption.
To achieve the above-mentioned object, the CDMA receiver according to the present invention comprises a high speed adder, a register group, first and second code generating means, first and second switches, first and second multipliers, and first and second slow speed adders.
The high speed adder adds a signal obtained by demodulating a received signal to a first accumulated value. The register group comprises as many first registers as the number of values that by a spreading code of a user signal may take on. Each of the registers of the group is reset for one symbol period. The first code generating means sequentially and repetitively generates a spreading code corresponding to a particular user signal.
The first switch receives a signal from the high speed adder and supplies the signal to one of first registers corresponding to a value being applied thereto from the first code generating means. The second switch selects a value stored in the one of the first registers corresponding to the value of the spreading code being applied thereto from the first code generating means to output the value as a first accumulated value.
The number of the first multipliers is equal to the number of the first registers included in the register group. Each of the first multipliers multiplies each value stored in one of the first registers by the value of the complex conjugate number of the value of the spreading code corresponding to a particular user signal associated with the one of the first registers. The first slow speed adder adds signals outputted from the first multipliers together. The second slow speed adder adds the values respectively stored in the first registers together. The second code generating means sequentially repeatedly generates the codes of the complex conjugate number of a spreading code corresponding to a common pilot signal. The second multiplier multiplies the added value at the second slow speed adder by the value of the code generated at the second code generating means.
In the present invention, integration for one symbol period is performed for each value of the spreading code corresponding to the particular user signal, by the use of the high speed adder, the first and second switches, and the register group, and the resultant values are once stored in the respective first registers of the register group and then despread is performed in accordance with respective spreading codes. As a result, an adder with a slow operational speed can be employed as the first slow speed adder for addition of the values from the first multipliers and the second slow speed adder for addition of the values of the first registers. Therefore, the common pilot signal and the user signal can be despread with only one high speed adder, thereby reducing an amount of power consumption.
According to an embodiment of the present invention, the CDMA receiver further includes a third slow speed adder and a second register. The third slow speed adder adds an output signal from the second multiplier to a second accumulated value. The second register stores an output signal from the third slow speed adder for one chip and then outputs the signal as the second accumulated value.
The present invention is thus applicable to a case in which even the symbol rate of the common pilot signal is not equal to the symbol rate of the user signal.
According to another embodiment of the present invention, the received signal from a transmitter is spread using QPSK (Quadrature Phase Shift Keying) and the register group includes four first registers.
The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.